This is regarding an urgemt position with our one of estemed clients.
Role: Physical Design Engg.
Exp Required: 5- 7 (or 7+)
Location: Hyderabad
Job Description:
Physical Design
Position: SDE/MTS and above
Positions Open: Multiple
Minimum Exp: 5 years (7+ years preferred)
Key Responsibilities:
The position is for a Physical Design Engineer in the AMD PD group catering to building the next generation fusion SoCs and discrete graphics processors. Fusion programs cater to the next gen compute requirements bringing in CPU, GPU and other functions on an integrated monolithic die. This position requires interface with large front-end design teams in US, Canada, Shanghai and India, mentoring new hires and owing an entire chip or portion of the chip from RTL/gates to tapeout.
The Physical Design Engineer will be responsible for 1. full chip activities covering floorplanning, clocking, budgeting, timing, verification etc., and/or 2. block level physical design activities which includes: floor planning, placement, scan-reordering, clock tree synthesis, in place optimization, routing, timing analysis/closure, ECO tasks (timing, functional, noise based ECOs), design rule checks (DRC), and Layout vs. Schematic (LVS) checks, low power solution development etc. In addition to this, he/she will also be participating in Physical design flow development/upgrade by continuously working with internal design teams and CAD vendors.
Job Requirements:
•Understanding Verilog HDL
•Understanding Deep Submicron effects such as 90nm and below
• Understanding OCV, DFM, DFY
• Excellent Block level and Full-chip physical design skills
• Self-motivated, leadership skills and experience working with global teams
•Minimum 5 years of ASIC physical design experience
•Back ground of ASIC Physical Design: Floor planning, Clock Tree Synthesis, P&R, extraction, EM/IR Drop Analysis, timing and Signal Integrity closure, physical verification, low power implementation etc
•Hands on experience and expertise in Cadence, Synopsys, Magma or Mentor Physical Implementation Tools
•Should have participated in a minimum of 3 fullchip tapeouts
If interested pls share your updated CV at ashu@inficaretech.com ASAP and I will get back to you immidiately.
Regards,
Ashu Vasdev
Inficare Tech
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Role: Physical Design Engg.
Exp Required: 5- 7 (or 7+)
Location: Hyderabad
Job Description:
Physical Design
Position: SDE/MTS and above
Positions Open: Multiple
Minimum Exp: 5 years (7+ years preferred)
Key Responsibilities:
The position is for a Physical Design Engineer in the AMD PD group catering to building the next generation fusion SoCs and discrete graphics processors. Fusion programs cater to the next gen compute requirements bringing in CPU, GPU and other functions on an integrated monolithic die. This position requires interface with large front-end design teams in US, Canada, Shanghai and India, mentoring new hires and owing an entire chip or portion of the chip from RTL/gates to tapeout.
The Physical Design Engineer will be responsible for 1. full chip activities covering floorplanning, clocking, budgeting, timing, verification etc., and/or 2. block level physical design activities which includes: floor planning, placement, scan-reordering, clock tree synthesis, in place optimization, routing, timing analysis/closure, ECO tasks (timing, functional, noise based ECOs), design rule checks (DRC), and Layout vs. Schematic (LVS) checks, low power solution development etc. In addition to this, he/she will also be participating in Physical design flow development/upgrade by continuously working with internal design teams and CAD vendors.
Job Requirements:
•Understanding Verilog HDL
•Understanding Deep Submicron effects such as 90nm and below
• Understanding OCV, DFM, DFY
• Excellent Block level and Full-chip physical design skills
• Self-motivated, leadership skills and experience working with global teams
•Minimum 5 years of ASIC physical design experience
•Back ground of ASIC Physical Design: Floor planning, Clock Tree Synthesis, P&R, extraction, EM/IR Drop Analysis, timing and Signal Integrity closure, physical verification, low power implementation etc
•Hands on experience and expertise in Cadence, Synopsys, Magma or Mentor Physical Implementation Tools
•Should have participated in a minimum of 3 fullchip tapeouts
If interested pls share your updated CV at ashu@inficaretech.com ASAP and I will get back to you immidiately.
Regards,
Ashu Vasdev
Inficare Tech
you may also like: MOST READ
1 comment:
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